@stman @patrislav I know, but #Helmholtz is an established research institution and they certainly need someone who can help them ontheir #FPGA-based systemsnto handle the sheer amount of data from their syncrotron particle accelerator ( @DESY ).
Plus I'm confident you'd rather want to work with an ethical employer doing science...
What github would I submit an issue to for an issue that affects the #GameGear #FPGA on the #analogue #pocket? Is there a "default" core that runs when you run it off cartridge that's different from if I load in an emu? Issue is in both, fwiw, so it has to be the FPGA (save corrupts it) not my cart or rom
Nobody seems familiar with my problem so maybe it only affects shining force, but it's 100% consistent and very frustrating
@patrislav @DESY ich kann @stman empfehlen.
Der hats echt drauf in Sachen #FPGA!
Bin mir sicher E13 wäre für den in Ordnung...
https://chaos.social/@patrislav/114074775578668422
Just leaving this here for reasons.
```
for f in **/*.xdb; do
echo $f
KEY=$(openssl kdf -kdfopt digest:SHA1 -kdfopt pass:$(basename $f .xdb) -kdfopt hexsalt:68f40c2a59 -kdfopt iter:1 -keylen 32 PBKDF2 | sed -e 's/://g')
openssl aes-256-cbc -K $KEY -iv d750a6297358021ea094cc46f112cef3 -d -in $f | tail -c+65 > $f.xml
done
```
Macintosh Plus/SE core has been updated on MiST 
=== plusToo_250310.rbf ===
- Fix scancode for up-arrow and numpad key mappings (by robinsonb5)
- Fix sound with direct VIA control (by darylrichards)
- Control the Caps Lock LED on the keyboard
https://github.com/mist-devel/mist-binaries/tree/master/cores/plus_too
Oh falls ihr wegen der Arbyte oder wegen Toy Projekt weg von Asien und US Silizium kommen wollt, schaut Euch mal den #cva6 an: Ist ne 6-stage pipeline #riscv (32/64bit) Implementierung die #fpga und #asic ready und gut verifiziert ist. Basiert auf der Arbeit der ETH Zürich, wurde dann von Thales aus Frankreich weiter entwickelt und wird nun durch die OpenHW Group betreut - also nen echtes Europa Dings:
PC Engine/Turbografx (which supports the base system, CD-ROM² up to Arcade Card, and Supergrafx systems) core has been udpated on MiST and Sidi 
=== tgfx16_250306.rbf ===
Latest SRG320 commits :
VDC :
- Fix rendering for 7M resolution mode
- Fix timing of sprite evaluation
MiST: https://github.com/tdelage26/mist-binaries/tree/master/cores/pcengine
Sidi: https://github.com/tdelage26/SiDi-FPGA/tree/master/Cores/Console/PCE
Nice! nextpnr-xilinx in the #openxc7 #opensource #FPGA toolchain now can place and route a #LiTeX GTX transceiver test design.
Sitze nun im Zug (:wave: Hannover) und bin remote bei Anne Beamline eingeloggt und programmiere weiter am #FPGA rum.
Meine mobile Workstation steht oben auf unserem 3D-Röntgenmikroskop; die vom Ingenieur steht unten auf dem Fußboden, er macht vom Institut aus Interferometer-Messungen.
Dabei schauen wir beide auf den gleichen Motor, stzrot: die Rotation für die #Röntgentomographie.
Алгоритм межкадровой разности на FPGA стереокамере
В этой статье я расскажу о продолжении работы над своим проектом стереокамеры на базе FPGA Gowin. В последней версии я добавил блок расчета попиксельной межкадровой разницы, используя встроенную в один корпус с FPGA SDR SDRAM память
Der #FPGA lief gut durch, ∃ Logdatei mit 29.385.185 Zeilen.
Die erste Spalte soll einfach nur hochzählen (wenn Zahlen fehlen = Fehler).
awk '{print $1-NR;}' tomotrg25.log | sort -n | uniq -c
… zieht von der Zahl in der ersten Spalte ($1) die Zeilennummer (NR = number of records) ab, dann wird sortiert, dann werden identische Zeilen zusammengefasst/gezählt.
Weil die Werte tatsächlich aufsteigend sind: $1-NR = const und diese Konstante kommt 29385185 mal vor 
Gee! #apicula learned how to feed frequency to PLL input from CLKDIV2 frequency divider!
The difficulty was that the CLKDIV2 is not capable of feeding a signal to general purpose wires and special wires for high frequency clocks had to be dealt with. (demonstrating this is very difficult btw)
Placing GTX bels already seems to work.
Nice. #openXC7 #opensource #FPGA toolchain.
Currently working on fixing this: https://github.com/zerkman/zest/issues/27
Precise timing comparisons with the real hardware led me to figure out that that the wrong timing in colour palette changes wrt. the actual pixel output is caused by missing intermediate registers at the output of the shifter. Fixing this solved the wrong colours issue, but led to pixel shifting showing that the current state of video signal generation is wrong. This part also needs fixing.
No skips - all wires are routed correctly and all dividers are working properly, division ratio changes.
5 CLKDIV2 and CLKDIV are running on this weird variant of the GW1NR-9. I still have GW1N-4 left, but I don't have this board, so there will only be a compiled variant.
More pics in my house and around the neighborhood using #gameboycamera and my #Gameboy Color
#pixelart #retrogame #retrogamer #nintendo #modretro #analougepocket #nintendo #lowres #fpga #gbc #gb #photography #gameboyphotograhy #photos #bwphotos
ok, after much hassle I managed to get an SPI Peripheral working in VHDL on my FPGA.
It receives 32 bits, and sends it back the next time it receives data.
It felt way more complicated than it needed to be, not sure why. But then everyday is a school day.
#FPGA
I often see the question: Is it possible to be an #FPGA freelancer?
I think it's difficult, but I don't have the experience. What is your opinion/experience?
